ASIC/SoC Development Services
Reducing time-to-market, securing tape-out, integrating complex IPs, optimizing power consumption or cost: our teams support you at every stage of the ASIC/SoC development cycle, with tailored solutions and proven expertise.
On this page:ASIC/SoC Engineering
Challenging projects, tailored solutions
As specialists in ASIC and SoC development (digital, analog, and mixed-signal), we support the development of your products by relying on the most widely used market architectures (Arm, RISC‑V, x86, MIPS) and the most advanced silicon technologies.
Our expertise spans a wide range of applications, from automotive and high-performance computing to IoT, aerospace, telecommunications, and more.
Your vision, our expertise: delivering electronic solutions of excellence
Why choose ADVANS Group for your ASIC/SoC development project?
Developing an ASIC or a SoC is a strategic challenge: it requires expertise, discipline, flexibility, and full mastery of the underlying technologies.
At ADVANS Group, we support you effectively, whatever your challenges — performance, power consumption, cost, reliability, or time-to-market.
Do you have a specific need or a project to launch? Let’s discuss it today.
Expertise
We develop ASICs and SoCs for leading international semiconductor companies, as well as Tier‑1 and Tier‑2 players across a wide range of industries.
Confidentiality
Our commitment to quality and confidentiality is reflected in a management system compliant with ISO 9001, ISO 14001, and ISO 27001 standards (for more details, see About > Certifications page).
Partnerships
We work with technology leaders such as Altera, Arm, AMD, Cadence, Microchip, Synopsys, and ST to provide our customers with privileged access to the best technologies and tools on the market.
Engagement Models
We offer flexible engagement options tailored to your needs: consulting and expertise, competence centers, service centers, and fixed-price projects.
Customized Solutions
We develop, with you or for you, ASICs or SoCs tailored to your constraints in terms of performance, power consumption, cost, and reliability.
Design centers
From our network of design centers in Europe, we manage your projects with close technical and operational proximity.
Engagement models tailored to your technical and business challenges
Expertise, flexibility, and innovation
We offer a range of engagement models to meet our customers’ needs.
Depending on the project scope and execution framework, ASIC/SoC development projects may be eligible for the French Research Tax Credit (CIR) or Innovation Tax Credit (CII). These schemes can provide tax incentives for R&D and technological innovation activities.
For any request, feel free to contact us.
Expertise, consulting
Our technical experts and consultants are involved in high value-added assignments. Resources are managed by our business managers, while you remain responsible for delivery and project management.
Competence Center
We set up a dedicated team of engineers. Resources are managed by our business managers, while you remain responsible for delivery and project management.
Service Center
As part of a service center, in addition to setting up and managing a team of specialized engineers, we take responsibility for delivery as well as for meeting cost, quality, and schedule objectives. We commit to results on activities defined in a catalog of units of work.
Fixed-Price Project
Based on a set of specifications, we deliver the project in compliance with our cost, quality, and schedule commitments. Our design offices handle all phases of execution across a wide range of projects, from single-discipline developments to cross-functional projects involving numerous technological interactions.
Strategic alliances for cutting-edge solutions
Technology partner ecosystem
We have established partnerships with market-leading companies.
The result is easier access to their latest innovations, advanced training for our engineers, and increased efficiency for our customers’ projects.
Altera ASAP Program Partner
A partnership focused on FPGA and SoC solutions within the ASAP (Altera Solution Acceleration Partner Program). This partnership validates our experience and expertise on Altera FPGA platforms.
AMD Adaptive Computing Partner
A partnership focused on FPGA and SoC solutions based on former Xilinx products. This partnership certifies our experience and expertise on AMD FPGA platforms. We can also certify our engineers on AMD technologies.
Arm Approved Design Partner
We provide Arm customers with integrated circuit design services (IP, ASIC, SoC, FPGA) for Arm cores, including dedicated and cost-optimized solutions.
Cadence Connections Verification Alliance
With many years of experience in reusable VIPs, we help accelerate the adoption of new technologies and improve the productivity of verification teams.
Microchip Approved Design Partner
A partnership focused on FPGA and SoC solutions based on former Actel and Atmel products. This partnership certifies our experience and expertise on Microchip FPGA platforms.
STMicroelectronics Authorized Partner
As an STMicroelectronics Authorized Partner, we accelerate STM32 developments (edge AI, IoT, low power) with direct access to ST experts to secure proofs of concept and prototypes.
Synopsys Emulation Training Partner
An ASIC emulation partnership based on Synopsys ZeBu. This partnership validates our experience and expertise in ASIC emulation using the Synopsys ZeBu platform.
Technical support across the entire development cycle
From concept to silicon: end-to-end support throughout the ASIC/SoC development cycle
Our teams are involved across the full ASIC/SoC development cycle, leveraging proven methodologies, state-of-the-art tools, and multi-industry expertise. With full control of the complete flow, we ensure performance, reliability, and optimized time-to-market.
From concept to silicon: an architecture designed to last
Design
Our engineers are involved from the very first stages of ASIC/SoC development. From architecture definition to logic synthesis, each phase is designed to ensure performance, reliability, and manufacturability of the chip.
We master high-level architectures, subsystem integration, IP block management, power, clock, reset, and security strategies, as well as testability constraints addressed from the early design phases.
High-level architecture
Definition of functional blocks, interfaces,
global constraints, and control strategies
(clock, reset, power, security).
Subsystem integration
Assembly of IP blocks & functional
modules within a coherent architecture,
with management of interactions & constraints.
IP block design
Development of dedicated digital IP blocks
tailored to project requirements, with consideration
of performance, area, & power consumption.
Memory partitioning, FSM
Organization of modules and submodules,
design of finite state machines (FSM),
selection of memory types and buffering
techniques.
Clock and reset management
Design of clock and reset trees,
implementation of clock gating,
synchronization across clock domains.
DFT implementation
Integration of test structures (scan, BIST, MBIST)
early in the design phase to facilitate validation
and production.
RTL coding
RTL coding in compliance with coding rules,
synthesis constraints, and best practices
for readability and testability.
Logic synthesis
Transformation of RTL code into an optimized netlist
for the target technology, with result analysis
and equivalence checking.
Physical implementation
Digital place-and-route, analog and mixed-signal layout,
up to mask generation for manufacturing.
Design verification
Consistency checks (sanity checks),
coding rule verification, power estimation,
ATPG analysis.
Mastered design ecosystem
Languages, tools, and technologies
Proven languages, technologies, and tools used to design robust architectures optimized for the target technology.
HDL languages
- VHDL,
- Verilog,
- SystemVerilog.
Design tools
- Design Compiler (Synopsys),
- RC Compiler (Cadence),
- Spyglass (Lint, CDC),
- Magillem (IP-XACT environment management),
- Power Analyzer,
- Bitwise (register definition),
- GIT, ClearCase, DesignSync.
Technologies
ASIC Technologies:
- Bulk CMOS, BCD, SOI, FinFET – from 500 nm down to 2 nm.
Foundries:
- TSMC, GlobalFoundries, STMicroelectronics, TowerJazz, Xfab, UMC…
Scripting languages
- Python,
- TCL,
- Perl.
Rigorous methods, industry standards
Methods & standards
Our design approach is based on structured methodologies and strict compliance with critical standards, ensuring quality from the very first lines of RTL code.
Methods
- V-model lifecycle,
- Agile methodology,
- RTL coding guidelines,
- Design flow validation (synthesis, equivalence checking, power estimation),
- RTL code reviews,
- RTL coverage,
- Design checklists.
Standards
- ISO 9001 (development and project management processes),
- ISO 26262 (automotive functional safety),
- DO‑254 (avionics),
- EN 50128 (railway).
From concept to silicon: validate before manufacturing
Virtual verification
Virtual verification ensures that the design behaves as expected before entering production. Our teams deploy advanced test environments to detect issues as early as possible in the development cycle, using simulation or formal verification.
We operate at all levels — IP, subsystem, SoC — using proven methodologies (UVM, assertions, coverage) and industry-standard tools.
Verification plan definition
Review of functional specifications,
definition of metrics, drafting of the test plan,
and validation by a technical review board.
Testbench architecture
Design and development of the verification environment,
including testbench components,
their integration, and maintenance.
UVM verification
Deployment of the UVM methodology for
verification environments: architecture,
development, maintenance, and improvement of
functional coverage.
Test suite development
Creation, documentation, and debugging of test cases,
with reuse of third-party components where relevant.
RTL and post-synthesis simulation
Execution of RTL, gate-level, and power-aware simulations,
with coverage analysis and regression management.
Embedded software verification
Validation of bootloader, firmware, boot code,
and user applications in
multi-core environments.
AMS verification
Analog modeling, model calibration,
mixed-signal simulation, verification of ABIST structures
and parasitic effects.
Validation criteria
100% coverage, 100% regressions, 100% checkers,
verified verification checklist,
completed verification review.
Mastered verification ecosystem
Languages, tools, and technologies
Specialized languages, technologies, and tools to secure complex designs and accelerate time-to-market.
HDL languages
- SystemVerilog,
- Verilog,
- VHDL.
Verification methodologies
- UVM,
- Assertions (SystemVerilog Assertions, PSL),
- Functional and structural coverage,
- Formal verification,
- Power-aware verification.
EDA tools
- ModelSim,
- Cadence Incisive / Xcelium,
- Synopsys VCS,
- Spectre, APS, XPS MS,
- AMS Designer,
- ADE-L / ADE-XL,
- Virtuoso Schematic Editor,
- Hierarchy Editor,
- vPlaner (verification planning),
- vManager (regressions and coverage).
Scripting languages
- Python,
- TCL,
- Perl.
AMS languages
- Verilog-AMS,
- eeNet.
Software languages
- C,
- ARM assembly,
- e/Specman.
Advanced methods, ensured compliance
Methods & standards
Our verification practices are built on industry standards and critical norms specific to the targeted sectors.
Methods
- UVM,
- eRM,
- Formal verification,
- Coverage-driven verification,
- V-model lifecycle.
Standards
- ISO 26262 (automotive),
- DO-254 (avionics),
- EN 50128 (railway),
- SIL (IEC 61508).
From concept to silicon: ensuring compliance through tape-out
Physical validation
We support our customers through the final stages of ASIC/SoC development. Our teams handle physical validation to ensure timing, power, area, and reliability constraints are met, before and after manufacturing.
We work on both pre-silicon (emulation, virtual test benches) and post-silicon phases (bring-up, debug, electrical and functional validation), in both digital and analog environments.
Test definition
Creation of the test list, specifications,
descriptions, and validation scenarios.
Driver development
Writing drivers to control interfaces
(UART, SPI, I2C, DMA, interrupts…) and
control modules.
Pre-silicon validation
Emulation of the design behavior on
emulation platforms (Palladium, Veloce, ZeBu),
functional and timing verification.
Post-silicon validation
Board bring-up, debug, electrical measurements,
functional and thermal validation,
robustness and stability testing.
Analog validation
Testing on DC/DC converters (Buck, Boost, Flyback,
SEPIC up to 2.5 A), LDOs up to 500 mA, PMICs,
sensors, mixed-signal interfaces.
Security and reliability
Validation of security modules (HSM, crypto),
verification of protection against packet loss
and communication errors.
Mastered implementation ecosystem
Languages, tools, and technologies
Measurement tools, emulation platforms, and automated test benches to turn a logical design into a circuit compliant with manufacturing requirements.
HDL languages
- VHDL,
- Verilog,
- SystemVerilog.
Scripting languages
- Python,
- TCL.
Software languages
- C,
- Arm assembly.
Validation tools
Emulation:
- Palladium, Veloce, ZeBu.
Instrumentation:
- Oscilloscopes (2 GHz, T3DSO2354A, T3DSO1204), SPD3303X power supplies, SDM3065X multimeter, AWG SDG2122X signal generators.
Analyzers:
- VN5650 (Ethernet + CANFD), VN1670 (CANFD + LIN + CANXL).
SMU:
- Keithley 2440.
Electronic load:
-
- BK Precision 8600B.
Thermostream:
-
- Thermal testing
Test software:
-
- LabVIEW.
Technologies & Layout
Silicon technologies:
- CMOS,
- FinFET.
Methodologies:
- DRC,
- LVS,
- ERC,
- DFM,
- EM/IR,
- STA,
- DFT.
Proven methods, certified quality
Methods & standards
Our physical validation processes rely on industrial methodologies and strict standards to ensure the reliability of the delivered silicon.
Methods
- STA (Static Timing Analysis),
- DRC/LVS/ERC,
- DFT/BIST,
- Post-silicon bring-up and debug,
- V-model lifecycle.
Standards
- ISO 9001 (development and project management processes),
- ISO 27001 (data security),
- ISO 26262 (functional safety),
- DO-254 (physical validation).
Innovative solutions to design and secure your SoCs
Advanced architectures and early validation
ADVANS Group integrates the latest technological advances into its ASIC/SoC projects, including chiplet architectures and emulation platforms. These approaches address growing requirements in terms of performance, reliability, and time-to-market.
Chiplets: modularity and performance
Chiplet architectures make it possible to distribute SoC functions across multiple interconnected blocks. This approach improves scalability, reduces manufacturing costs, and facilitates the integration of heterogeneous technologies.
Emulation: accelerated validation
We use high-performance emulation platforms (e.g., Synopsys ZeBu) to test interactions between IP blocks, validate architectures, and identify risks before tape-out.
Co-design and vérification
Emulation is part of a co-design and co-verification approach, closely aligned with our teams specialized in digital and AMS verification.
Engineering solutions for all industrial sectors
ADVANS Group operates across a wide range of industrial sectors, delivering advanced engineering solutions tailored to the specific needs of each domain. Our expertise covers aerospace, automotive, defense, energy, IoT, medical, semiconductors, telecommunications, and many others.
Our expertise in action on high-value technology projects
Project references
ADVANS Group supports its customers on complex and strategic projects, from design through physical validation. Below are a few examples of projects delivered by our teams in demanding sectors such as automotive, high-performance computing, and IoT.
The examples below are anonymized to protect customer confidentiality.
HPC: Front-end processor design
Design and verification of a CNN subsystem for an ASIC target, compatible with multiple algorithms. Generic architecture, RTL development, formal verification, testbenches, and regressions. FPGA prototyping and embedded software verification. Project delivered as a competence center engagement, with controlled power, area, and performance KPIs.
SoC design and middle-end for IoT
Architecture, design, and verification of a general-purpose processor for high-performance computing. Integration of complex IPs (HBM, PCIe, DDR), distributed power, clock, and reset management. UVM methodology, formal verification, functional and code coverage. European collaborative project with 27 partners, managed using Agile Scrum.
STM32-based IoT SoC Development
Design and middle-end of an IoT SoC integrating analog and RF IPs. Hierarchy creation, IP instantiation and interconnection, C-based test adaptation, simulation, and power analysis. Implementation of SV-UVM verification, functional coverage, and emulation. Multisite project led by ADVANS Group.
5G modem and network subsystem development
Full design of a 5G modem and a network subsystem, including parsing, classification, compression, clock synchronization, and signal processing. FPGA and ASIC implementation, UVM/Specman verification, microarchitecture development, RTL coding, and synthesis. Three-year project delivered by specialized teams in Serbia.
Secure automotive SoC development
Design and integration of a multi-core SoC with analog subsystems, SPI, UART, CAN interfaces, and functional safety blocks. ASIL requirement implementation, RTL development, digital integration, functional verification, and timing constraint management. Project delivered using Agile methodology.
Automotive SoC Verification
End-to-end verification of an embedded SoC, covering IPs, subsystems, and the full system. Deployment of a UVM environment, development of testbenches, sequences, and C-driven tests. Objective: secure communications between sensors, cameras, and central supervision while ensuring robustness against packet loss. Multisite project with technical leadership, milestone tracking, and full functional coverage.
RF SoC verification for critical applications
Complete verification of a multi-chip SoC integrating an Arm core and an RF die for automotive and medical applications. Single UVM environment covering digital, AMS, software, and post-synthesis verification. Testbench development, functional coverage, firmware, and RF interface verification. Multisite project with a dedicated team over four years.
Battery management system verification
Digital and AMS verification of battery management ICs for electric vehicles. Wreal modeling, TopCell verification, fault injection, functional coverage, and software verification. ASIL D–compliant project delivered in a multisite environment using UVM tools, FlexVC VIP, and advanced methodologies.
AMS verification for automotive radar
Analog and mixed-signal verification of radar transceivers for premium vehicles. Modeling, AMS simulation, non-regression verification, and functional validation. Long-term project in a customer environment using Virtuoso, SimVision, vManager, and Calibre. Dedicated team in Serbia across multiple RF-CMOS chip generations.
Secure NFC controller verification
Digital verification of a Cortex-M–based NFC SoC for mobile and secure payment applications. Verification plan development, functional and code coverage, IP verification for I2C, I3C, and TLV protocols. Competence center project with up to six dedicated engineers.
PMIC Verification for Critical Applications
Verification of PMIC and SBC devices for automotive, IoT, and industrial applications. Formal verification, traceability with DoorsNG, functional coverage, regressions, and UVM environments. Project delivered in Serbia with a dedicated team, in a customer environment, across multiple product generations.
Cellular transceiver layout in FinFET
Physical layout of RF blocks in 7 nm and 3 nm FinFET technologies. Floorplanning, DRC/LVS/DFM verification, technical coordination, and resource management. Fully outsourced project delivered using Virtuoso and Calibre in a secure customer environment.
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Your questions about ASIC/SoC development – Answers from ADVANS Group
Frequently Asked Questions (FAQ)
Are you wondering about the technical challenges, key stages, or engagement models related to ASIC and SoC development? This FAQ brings together answers to the most frequently asked questions to help you better understand our expertise, methods, and the solutions we offer.
ASIC / SoC definitions
What is an ASIC and a SoC?
An ASIC (Application-Specific Integrated Circuit) is an integrated circuit designed for a specific application.
A SoC (System on Chip) integrates multiple functions on a single chip — such as the processor, memory, interfaces, and dedicated hardware blocks — in order to optimize performance, power consumption, and cost.
Differences between ASIC, SoC, and FPGA
What is the difference between an ASIC, a SoC, and an FPGA?
An ASIC is a circuit dedicated to a specific function, optimized for high-volume production.
A SoC integrates multiple complete functions on a single chip.
An FPGA is reconfigurable, making it suitable for prototyping or low-volume production, but it is generally less performant and more power-hungry than an ASIC or a SoC.
Develop an ASIC or a SoC?
In which cases should you develop an ASIC or a SoC?
Developing an ASIC or a SoC is relevant when performance, power consumption, security, or unit cost constraints are critical, particularly for products manufactured in medium to high volumes.
Virtual verification
What is virtual verification in an ASIC/SoC project?
Virtual verification involves simulating and verifying the functional behavior of an ASIC or a SoC before manufacturing, in order to detect issues as early as possible.
It relies on test environments that validate IPs, subsystems, and complete systems.
Physical validation
What does physical validation of an ASIC/SoC involve?
Physical validation aims to verify that the circuit meets timing, power consumption, area, and reliability constraints, both before and after manufacturing.
It includes pre-silicon and post-silicon test phases to ensure the correct operation of the actual silicon.
Industry sectors
Which industrial sectors use ASICs or SoCs?
ASICs and SoCs are used across many industrial sectors subject to stringent requirements in terms of performance, power consumption, reliability, or security.
They are widely used in automotive, aerospace and space, telecommunications, HPC infrastructures, the Internet of Things (IoT), medical devices, defense, and energy.
Tools and languages used
Which tools and languages are used for ASIC/SoC development?
ASIC and SoC development relies on specialized tools for design, verification, and validation.
The most commonly used hardware description languages are SystemVerilog, VHDL, and Verilog, along with C/C++ for certain modeling or test-related aspects.
Design and verification environments typically rely on industry-standard tools for simulation, synthesis, place-and-route, and functional and timing verification.
Project duration
What is the typical duration of an ASIC/SoC development project?
The duration depends on the complexity of the project. A full development cycle can range from 6 to 24 months, including specification, architecture, design, verification, and physical validation.
Partial outsourcing
Can part of an ASIC/SoC development be outsourced?
Yes, it is possible to outsource all or part of the ASIC or SoC development cycle.
Certain stages, such as functional verification, pre-silicon validation, or post-silicon validation, can be entrusted to specialized teams, depending on project needs, available internal resources, and the maturity level of the project.
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